As integrated circuits become faster, eliminating timing skew (or signal arrival time) among signals propagating along high speed printed circuit boards becomes increasingly important. Many techniques have been proposed for handling timing skew, but they all involve substantial costs and/or complex manufacturing techniques.
For example, U.S. Pat. No. 5,260,892 describes a method and apparatus for manufacturing an improved Dynamic Random Access Memory (“DRAM”) electrical signal interconnect structure having special application to Single In-Line Memory Modules (“SIMMs”). The structure contains an on-board buffer for deriving time-critical signals from a single source. The conductor structure further includes trace signal routes that allow for approximately equivalent minimum distance signal line lengths. The device further includes vias connecting the front and rear surfaces of the SIMMs, resulting in a high speed, high density SIMM with clean rising and falling edges. The conduction pattern, however, has to be carefully laid out and is therefore relatively expensive to implement.
Accordingly, there is a need for an improved method and system that will reduce the timing skew for signals, such as clock or data signals, propagating along a printed circuit board, such as one used in a memory module. There is also needed a new and improved method that will reduce the cost of production and manufacture of memory modules, as well as a method and system that will allow more relaxed tolerances in the manufacture of such memory modules.